Implementação reduzida de MIPS-32 monociclo em system verilog

Abstract

This paper presents an implementation of the basic processing unit of a processor derived from MIPS 32, with a reduced instruction set and single-cycle design. It does not include privileged instructions and functionalities like interrupt handling and I/O support. The memory modules were substituted for mock units for the execution of the integration tests. The tests were coded in Python and executed using the framework cocotb, due to its ease of use. The architecture was implemented using the language SystemVerilog and compiled using both Icarus Verilog and Verilator. Despite the project not having been synthesized, the simulations demonstrated proper functioning and produced accurate results.